Block diagram / concept image of LAPU: vector registers, matrix banks, fixed-point compute units

LAPU — Linear Algebra Processing Unit In Progress

128-bit complex fixed-point • matrix/vector ops • VHDL • cocotb benches

LAPU is a compact, programmable accelerator designed for high-speed manipulation of large square matrices and vectors, implemented in VHDL. Unlike traditional approaches that rely on memory to store matrix data, LAPU encodes the matrix directly in hardware through a specialized unit called the matrix bank. Combined with built-in linear algebra operations, a 128-bit native representation of complex numbers, and extensive SIMD (single instruction, multiple data) support, LAPU delivers accelerated, customizable computation on square matrices. Development is currently ongoing.

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